“CMOS” refers to both a particular style of digital circuitry design, and the family of processes used to implement that circuitry on IC “chips” or “die”. CMOS logic uses a combination of p-type and n-type metal-oxide-semiconductor field-effect transistors (MOSFETs) to implement logic gates and other circuits found in computers, telecommunication equipment, and signal processing equipment. Typical commercial CMOS ICs include millions (or hundreds of millions) of n-type and p-type MOSFETs.
Most CMOS IC manufacturers (aka, “fabs”) generate standardized process “flows” for generating CMOS ICs on monocrystalline silicon wafers. Each CMOS process flow includes a series of processing steps (e.g., material deposition, photolithographic exposure, and etching) that are required to produce a desired CMOS IC product. Standard CMOS process flows are typically developed to produce “normal” CMOS IC devices (i.e., CMOS IC devices that comprise mainly volatile n-type and p-type MOSFETS) using a minimum number of processing steps in order to minimize overall production costs. Significant effort is typically expended by each manufacturer to make their standard CMOS process flow as time and cost efficient as possible. Once a standard CMOS flow is optimized, it can typically be used to make a large number of CMOS IC designs merely by providing a different set of photolithography masks for each IC design, and then repeating the standard CMOS process flow using the selected set of photolithography masks.
Although most standard CMOS process flows facilitate the inclusion of non-MOSFET circuit components into the CMOS IC products, a problem arises when a circuit design requires a circuit component that cannot be produced by the standard CMOS process flow. In this case, particularly when several additional steps are required to produce a particular nonstandard circuit component, where each step requires a corresponding additional mask and associated, the CMOS process flow must be significantly modified at great expense to include the additional steps in order to produce the needed circuit component. It is therefore desirable to develop methods for producing the non-standard circuit component using the steps of the existing CMOS process flow, or using only a small number of additional process steps that can be included in the standard CMOS process flow with minimal effect on the standard CMOS circuit elements.
Non-volatile memory (NVM) or “floating gate” cells represent one type of non-standard circuit component that is often needed in large scale CMOS ICs. In contrast to volatile (aka primary storage) memory built of typical n-type and p-type MOSFETs which require continuous power to retain stored information, NVM cells are able to retain a stored state even when power to an IC is turned off, thereby allowing the IC to “remember” important operating conditions and information upon restart. Several types of NVM cells have been developed that can be produced with minimal changes to a standard CMOS process flow. One NVM cell that has a small floating gate capacitively coupled to the drain area is disclosed in U.S. Pat. No. 6,678,190. This NVM cell is a programmable read only memory comprising two serially connected P-type metal-oxide semiconductor (MOS) transistors, wherein the floating gate coupling to the source and drain is symmetric, and wherein a control gate is omitted because a special gate bias is not necessary in the programming mode. A problem with the PMOS NVM cells of U.S. Pat. No. 6,678,190 is that only a small portion of Vd is transferred to the floating gate, so that a subsequent erase operation is practically impossible, thus limiting the application of corresponding cells to OTP (one-time program) memories only.
What is needed is an NVM cell that is small to medium in size, exhibits high endurance (allows multiple cycling, i.e., program/erase operations), and can be produced using either a standard single-poly CMOS process flow (i.e., a CMOS process flow including only a single polysilicon layer), or a slightly modified single-poly CMOS process flow that adds only one or two additional masks to a standard CMOS process flow.